diff --git a/Makefile b/Makefile
index 4bb99ed4ba..f81f3ddc08 100644
--- a/Makefile
+++ b/Makefile
@@ -33,6 +33,7 @@ TEST_FILE = $(shell find ./src/test/scala -name '*.scala')
 
 MEM_GEN = ./scripts/vlsi_mem_gen
 MEM_GEN_SEP = ./scripts/gen_sep_mem.sh
+GIT_COMMITID_GEN = ./scripts/genGitCommitID.py
 
 CONFIG ?= DefaultConfig
 NUM_CORES ?= 1
@@ -148,6 +149,7 @@ test-jar:
 
 $(TOP_V): $(SCALA_FILE)
 	mkdir -p $(@D)
+	$(GIT_COMMITID_GEN) "-o" $(@D)
 	$(TIME_CMD) mill -i xiangshan.runMain $(FPGATOP)   \
 		--target-dir $(@D) --config $(CONFIG) --issue $(ISSUE) $(FPGA_MEM_ARGS)		\
 		--num-cores $(NUM_CORES) $(RELEASE_ARGS)
@@ -164,6 +166,7 @@ verilog: $(TOP_V)
 
 $(SIM_TOP_V): $(SCALA_FILE) $(TEST_FILE)
 	mkdir -p $(@D)
+	$(GIT_COMMITID_GEN) "-o" $(@D)
 	@echo -e "\n[mill] Generating Verilog files..." > $(TIMELOG)
 	@date -R | tee -a $(TIMELOG)
 	$(TIME_CMD) mill -i xiangshan.test.runMain $(SIMTOP)    \
diff --git a/scripts/genGitCommitID.py b/scripts/genGitCommitID.py
new file mode 100755
index 0000000000..9db135452d
--- /dev/null
+++ b/scripts/genGitCommitID.py
@@ -0,0 +1,61 @@
+#! /usr/bin/env python3
+
+import subprocess
+import argparse
+import os
+from textwrap import dedent
+
+def get_git_commit_sha():
+  try:
+    sha = subprocess.check_output(['git', 'rev-parse', 'HEAD']).decode('utf-8').strip()
+    return sha
+  except subprocess.CalledProcessError:
+    print("Error: This script must be run from a git repository.")
+    return None
+
+def check_if_status_dirty():
+  try:
+    lines = subprocess.check_output(['git', 'status', '-uno', '--porcelain']).decode('utf-8').strip()
+    return len(lines) != 0
+  except subprocess.CalledProcessError:
+    print("Error: This script must be run from a git repository.")
+    return None
+
+def generate_verilog(sha, dirty):
+  verilog_template = dedent("""
+    module CommitIDModule(
+      output reg [39:0] commitID, // 40-bit output for commit SHA
+      output reg        dirty     // if git status is dirty
+    );
+
+    initial begin
+      commitID = 40'h{sha};
+      dirty = 1'b{dirty};
+    end
+
+    endmodule
+  """)
+  return verilog_template.format(sha=(sha.upper())[0:10], dirty=int(dirty))
+
+def main(output_path):
+  sha = get_git_commit_sha()
+  dirty = check_if_status_dirty()
+  if sha:
+    verilog_code = generate_verilog(sha, dirty)
+    print("Generated Verilog Code:")
+    if not os.path.exists(os.path.dirname(output_path)):
+      os.makedirs(os.path.dirname(output_path))
+
+    filename = os.path.join(output_path, "CommitIDModule.sv")
+    # 将Verilog代码写入文件
+    with open(filename, 'w') as f:
+      f.write(verilog_code)
+    print(f"Verilog module has been created at '{filename}'.")
+  else:
+    print("Failed to get the git commit SHA.")
+
+if __name__ == "__main__":
+  parser = argparse.ArgumentParser(description="Generate a Verilog module with the current git commit SHA.")
+  parser.add_argument("-o", "--output", required=True, help="Output file path for the Verilog module.")
+  args = parser.parse_args()
+  main(args.output)
diff --git a/src/main/scala/xiangshan/backend/fu/NewCSR/CommitIDModule.scala b/src/main/scala/xiangshan/backend/fu/NewCSR/CommitIDModule.scala
new file mode 100644
index 0000000000..5435f92f45
--- /dev/null
+++ b/src/main/scala/xiangshan/backend/fu/NewCSR/CommitIDModule.scala
@@ -0,0 +1,11 @@
+package xiangshan.backend.fu.NewCSR
+
+import chisel3._
+import chisel3.experimental.noPrefix
+
+class CommitIDModule extends BlackBox {
+  val io = IO(noPrefix{new Bundle {
+    val commitID = Output(UInt(40.W))
+    val dirty    = Output(Bool())
+  }})
+}
diff --git a/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala b/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
index b1d6e1bde0..ff54daa44a 100644
--- a/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
+++ b/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
@@ -266,6 +266,12 @@ class NewCSR(implicit val p: Parameters) extends Module
 
   val permitMod = Module(new CSRPermitModule)
   val sstcIRGen = Module(new SstcInterruptGen)
+  val commidIdMod = Module(new CommitIDModule)
+
+  val gitCommitSHA = WireInit(commidIdMod.io.commitID)
+  val gitDirty    = WireInit(commidIdMod.io.dirty)
+  dontTouch(gitCommitSHA)
+  dontTouch(gitDirty)
 
   private val wenLegal = permitMod.io.out.hasLegalWen