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I have searched the previous issues and did not find anything relevant. 我已经搜索过之前的 issue,并没有找到相关的。
I have reviewed the commit messages from the relevant commit history. 我已经浏览过相关的提交历史和提交信息。
Describe the bug
After three operations on the mstatus register, using csrw, csrrw, and csrrs to modify mstatus, the use of the csrc instruction to clear certain bits did not work as expected. Detail please check asm code in the zip file below.
Here are screenshots:
Expected behavior
Since I am not aware of the initial value of mstatus in Xiangshan and NEMU, I cannot infer what the expected value should be. I ran spike got different value, so I am not sure whether NEMU is correct.
Before start
Describe the bug
After three operations on the
mstatus
register, usingcsrw
,csrrw
, andcsrrs
to modifymstatus
, the use of thecsrc
instruction to clear certain bits did not work as expected. Detail please check asm code in the zip file below.Here are screenshots:
Expected behavior
Since I am not aware of the initial value of
mstatus
in Xiangshan and NEMU, I cannot infer what the expected value should be. I ran spike got different value, so I am not sure whether NEMU is correct.To Reproduce
csrc.zip
Environment
Additional context
I suspect that the issue #3709 with the
fle.d
instruction may be related to thecsrr
instruction.The text was updated successfully, but these errors were encountered: