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module port附近有注释,会导致解析文档的port表格description列混乱 #78

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GarenZZ opened this issue Aug 20, 2024 · 0 comments
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bug Something isn't working high priority T1 or T0 level bug

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@GarenZZ
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GarenZZ commented Aug 20, 2024

  • 若存在header,会导致每个信号的描述都会有header
  • 若在某个信号右侧添加注释,会导致该行全部的文本出现在所有信号的描述

屏幕截图 2024-08-20 143511
屏幕截图 2024-08-20 143634
屏幕截图 2024-08-20 144454

@Nitcloud Nitcloud added bug Something isn't working high priority T1 or T0 level bug labels Aug 30, 2024
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Labels
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